Issues in High Frequency Noise Simulation for Deep Submicron MOSFETs

This paper proposes issues in highly accurate high frequency noise simulation for deep submicron MOSFETs. Unlike classical RF design, in which a given device with fixed characteristics is used, CMOS RF design permits selection of user specified device geometries as well as matching elements and bias conditions. Therefore, an exhaustive intrinsic noise modeling of MOSFETs across the entire operating condition is required. In order to capture the physics needed for accurate noise simulation of short-channel MOSFETs, a noise simulation tool needs the capability to exploit multi-dimensional device simulation in conjunction with process simulation. Further scaling of gate oxides introduces substantial gate leakage current due to the direct tunneling of electrons in the channel. It is expected that this current subsequently introduces shot noise current in the gate and the drain.